1. Field of the Invention
The disclosed technology relates generally to methods of manufacturing a semiconductor device, and more specifically to methods of manufacturing a dual work function semiconductor device.
2. Description of the Related Technology
CMOS technology utilizes NMOS transistors and PMOS transistors having different gate metals with different effective work functions. Generally, a CMOS process integration scheme employing high-k/metal gate technology can be “gate-first” or “gate-last,” depending on whether the gate electrode of a transistor is formed before or after the formation of transistor junctions. Different integration schemes face different fabrication challenges. In gate-first CMOS integration schemes employing the high K/metal gate technology, different effective work functions for NMOS and PMOS transistors are sometimes obtained using different capping layers or different metal stacks for the NMOS and PMOS transistors. In some technologies, the capping layers can comprise rare earth elements. In other technologies, the capping layers can comprise other elements such as Mg for the NMOS transistor and Al or Al2O3 for the PMOS transistor.
Patterning the cap layers of the transistors in gate-first CMOS integration schemes employing the high-k/metal gate technology introduces certain process integration challenges. For example, when different metal stacks are used for NMOS and PMOS transistors, the gate etch has to be performed simultaneously on different stack heights, or even on two totally different stacks. The difference in stack materials and/or stack heights can cause various problems. One such problem can arise during etching of the gates. For instance, the difference in stack materials and/or the stack heights can result in a first type of gate structure/material (e.g., NMOS or PMOS) to be completely etched prior to a second type of gate structure/material (e.g., PMOS or NMOS). As a consequence, upon completion of etching of the second type of gate structure/material, certain Si and STI regions originally covered by the first type of gate structure may be over-etched, resulting in recesses in the Si and STI regions. Another such problem that can also arise during etching due to the difference in gate stack/materials and/or the gate stack heights is the formation of a “foot” or a notch on one or both types of gate stacks. Therefore, there is a need for CMOS processes for integrating NMOS and PMOS transistors on the same substrate while minimizing the effects of these integration challenges.